@[email protected] to [email protected]English • 1 month agoWhich new Protocol or Standard are you most excited about?message-square52fedilinkarrow-up190arrow-down14file-text
arrow-up186arrow-down1message-squareWhich new Protocol or Standard are you most excited about?@[email protected] to [email protected]English • 1 month agomessage-square52fedilinkfile-text
minus-square@[email protected]linkfedilink22•edit-21 month agoIn principle it’s just "slimmer ARM!. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports. Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
minus-square@mvirtslink5•1 month agoI for one think we need a register for each unsigned integer, why is zero so special? :P Or if we can’t get that, at least every power of 2 and power of 2 minus 1. Maybe I can submit a proposal for risc-VI 🤣
minus-square@PetteriPanolink9•1 month ago Maybe I can submit a proposal for risc-VI 🤣 No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
minus-square@[email protected]linkfedilink3•1 month agoARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
minus-square@[email protected]linkfedilink3•1 month agoAren’t they more like a hybrid instruction set and architecture?
In principle it’s just "slimmer ARM!. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports.
Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
I for one think we need a register for each unsigned integer, why is zero so special? :P
Or if we can’t get that, at least every power of 2 and power of 2 minus 1.
Maybe I can submit a proposal for risc-VI 🤣
No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
I think a register for each of the primes should be enough.
ARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
Aren’t they more like a hybrid instruction set and architecture?