So, trying not to dox myself, I worked with the architect twice.
Knights Ferry was derived directly from Larrabee (GPU), P54Cs with pre-AVX-512, .
KNC was a die shrink with more cores. Both of these were PCIe accelerators only.
KNL had full Airmont Atom cores with smt4, basically meaningful cores with proper AVX-512. Also you could boot them with linux, or as a PCIe accelerator.
KNM jadded ML instructions, basically 8/16bit float and faster SIMD.
They cancelled KNH.
I interviewed some of the actual Larrabee guys, they were wild, there was a lot of talk about dynamic translation, they were trying to do really complex things, but when people talk like that it makes me think they were floundering on the software and just looking for tech magic solutions to fundamental problems.
Intel always dies when the software gets more complex than really simple drivers, it’s their achilles heel.
KNL also had the whole MCDRAM on package for basically HBM bandwidth, but that didn’t actually work very well in practice, again due to software issues (you have to pick where you allocate, and using it as an l4 cache was not always effective).
So, trying not to dox myself, I worked with the architect twice.
Knights Ferry was derived directly from Larrabee (GPU), P54Cs with pre-AVX-512, .
KNC was a die shrink with more cores. Both of these were PCIe accelerators only.
KNL had full Airmont Atom cores with smt4, basically meaningful cores with proper AVX-512. Also you could boot them with linux, or as a PCIe accelerator.
KNM jadded ML instructions, basically 8/16bit float and faster SIMD.
They cancelled KNH.
I interviewed some of the actual Larrabee guys, they were wild, there was a lot of talk about dynamic translation, they were trying to do really complex things, but when people talk like that it makes me think they were floundering on the software and just looking for tech magic solutions to fundamental problems.
Intel always dies when the software gets more complex than really simple drivers, it’s their achilles heel.
KNL also had the whole MCDRAM on package for basically HBM bandwidth, but that didn’t actually work very well in practice, again due to software issues (you have to pick where you allocate, and using it as an l4 cache was not always effective).