I’m aggregating some tutorials, libraries, and parts for the raspberry pi pico. I’m in the process of making a chiptune tracker on the pi pico and as I’ve been researching I’ve gathered a lot of links and stuff. So I figured I’d compile it into a public thread. Also its just a nice format to be able to go through myself. if someone could lmk if they know something similar that already exists that would be awesome & could potentially merge resources with it

  • ferric_carcinization@lemmy.ml
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    30 days ago

    This is about the pico 2, not the original, but would you know of a reason to use the RISC-V cores other than “Oh cool, it supports RISC-V now!”?

    I’ve only used the ARM cores, and from what I remember from the documentation, the RISC-V cores didn’t beat ARM ones in anything. If I remember correctly the RISC-V cores also had a few limitations, like lacking FPUs.

    Every single pico 2 build has two of both types of cores, so they have to have some use, right?

    I could somewhat understand it if you could use more than two cores at once, but you can’t.

    • paper_mint@retrolemmy.comOP
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      30 days ago

      I’m not goated enough to know about that, also I’ve never used the pico 2, but I’ll keep an eye out. I get the feeling that they’re just trying to push RISC-V forward which is cool of them. Or maybe there are some niche applications that need it?

      • ferric_carcinization@lemmy.ml
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        30 days ago

        I’m also interested in RISC-V, but it feels weird that the cores are included in every single pico 2.

        I guess that allows you to transition from ARM to RISC-V easier, but outside of hobby projects, I don’t see any reason to prefer the pico 2’s RISC-V cores over a RISC-V -only μC.

        I just wish that they’d give a reason to use it over ARM. As I understand it, currently it’s in practice just a less effective version of the ARM cores without a FPU. For example, something like advertising a cool extension ARM doesn’t have, or making a RISC-V-only version for a bit cheaper.