A ton of people. Anything aerospace, DoD, Space, or critical infrastructure. All those industries have to use VHDL to support legacy products from the 80s and 90s. At that point everyone is like, “Sure its 2025, by why switch to SystemVerilog? We already know VHDL.” and thus you got a whole army of engineers making next gen satellites, augmented reality headsets, etc. …… in VHDL 93.
Not really, HDL is HDL. At the end of the day, as long as you know what you want to do electrically then everything else is an exercise of translating that desire into VHDL, Verilog, or SystemVerilog. The only real hassle is creating test-benches and verification simulations. But at that point it’s discretionary towards the designer. A lot of tools coming from Intel, Xilinx, and Synopsys allow you to “black box” components. So a module written in VHDL can be incorporated into a design or test bench written in verilog and vis-versa. IMHO VHDL is still dominant because grey beard chief engineers throw a little hissy fit at design reviews when they learn the junior engineers did everything in verilog.
I do mostly c/c++ for an embedded product, but one of the modules in the system uses an FPGA programmed w/ VHDL. So I’ve gotten to do a few deep dives into that code in the past couple years.
It’s been decades since I’ve had to write new VHDL or Verilog though.
You work at IBM or something? Who even still uses VHDL?
A ton of people. Anything aerospace, DoD, Space, or critical infrastructure. All those industries have to use VHDL to support legacy products from the 80s and 90s. At that point everyone is like, “Sure its 2025, by why switch to SystemVerilog? We already know VHDL.” and thus you got a whole army of engineers making next gen satellites, augmented reality headsets, etc. …… in VHDL 93.
Is it such a hassle learning verilog if you know vhdl or vice versa?
Not really, HDL is HDL. At the end of the day, as long as you know what you want to do electrically then everything else is an exercise of translating that desire into VHDL, Verilog, or SystemVerilog. The only real hassle is creating test-benches and verification simulations. But at that point it’s discretionary towards the designer. A lot of tools coming from Intel, Xilinx, and Synopsys allow you to “black box” components. So a module written in VHDL can be incorporated into a design or test bench written in verilog and vis-versa. IMHO VHDL is still dominant because grey beard chief engineers throw a little hissy fit at design reviews when they learn the junior engineers did everything in verilog.
Lol, so much of the FPGA industry 🤣. Especially East coast of the US
I do mostly c/c++ for an embedded product, but one of the modules in the system uses an FPGA programmed w/ VHDL. So I’ve gotten to do a few deep dives into that code in the past couple years.
It’s been decades since I’ve had to write new VHDL or Verilog though.